View TS88915TMWDT70_3877705.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

visit our website: www.e2v.com for the latest version of the datasheet e2v semiconductors sas 2007 ts88915t low skew cmos pll clock driver tri-state 70 and 100 mhz versions datasheet 0854b?hirel?07/07 features vcc = 5v 5% military temperature range fully compatible with the ts68040 five low skew outputs ? five outputs (q0-q4) with ou tput-to-output skew < 500 ps each being phase end frequenc y locked to the sync input three additional outputs are available: ? the 2x_q output runs twice the system ?q? frequency ? the q/2 output runs at 1/2 the system ?q? frequency ?the q5 output is inverted (180 phase shift) two selectable clock inputs ? two selectable clock inputs are avai lable for test or redundancy purposes ? test mode pin (pll_en) provided for low frequency testing ? all outputs can go into high impeda nce (3-state) for board test purposes input frequency range from 5 mhz to 2x_q fmax three input/output ratios ? input/output phase-lo cked frequency ratios of 1:2, 1:1 and 2:1 are available low part-to-part skew ? the phase variation from part-to-part between the sync a nd feedback inputs is less than 550 ps (derived from the tpd specification, which defi nes the part-to-part skew) cmos and ttl compatible ? all outputs can drive either cmos or ttl inputs ? all inputs are ttl-level compatible lock indicator (lock) indica tes a phase-locked state description the ts88915t clock driver utilizes a phazed-locked loop (pll) technology to lock its low skew outputs? frequency and phase onto an input reference clock. it is designed to provide clock distribution for high performance microprocessors such as ts68040, tspc603e,tspc603p,tspc603r, pci bridge, ram?s, mmu?s. screening/quality this product is manufactured: based upon the generic flow of mil-std-883 or according to e2v-grenoble standard r suffix pga 29 ceramic pin grid array w suffix ldcc 2 8 leaded ceramic chip carrier
2 0854b?hirel?07/07 ts88915t e2v semiconductors sas 2007 1. introduction the ts88915t is a cmos pll clock driver using ph ase-locked loop (pll) technology. the pll allows the high current and low skew outputs to lock onto a single input and distribute it with essentially zero delay to multiple components on a board. the pll also allows the ts88915t to multiply a low frequency input clock and distribute it locally at a higher (2 x) system frequency. multip le 88915?s can lock onto a single reference clock, which is ideal for applications when a centra l system clock must be distributed synchronously to multiple boards (see figure 7-8 on page 15 ). figure 1-1. ts88915t block diagram (all versions) pll_en freq_sel oe/rst divide by two mux 01 (1) (2) m u x 1 0 feedback sync[0] sync[1] ref_sel m u x 0 1 phase/freq. detector ext. rec network (rc1 pin) voltage controlled oscillator charge pump/ loop filter lock 2x_q q0 q1 q2 q3 q4 q5 d q q r cp d q q r cp d q q r cp d q q r cp d q q r cp d q q r cp q/2 d q q r cp
3 0854b?hirel?07/07 e2v semiconductors sas 2007 ts88915t 2. pin assignments 2.1 29-lead pin grid array (pga) figure 2-1. 29-lead pga (bottom view) 2.2 28-lead ceramic leaded chip carrier (ldcc) figure 2-2. 28-lead ldcc (top view) 123456 a b c d e f ts88915t (bottom view) vcc gnd q4 fdbk syc0 vcca gnda rst q5 vcc q/2 gnd vcc q2 lock f/sl syc1 rc1 r/sl vcc q0 gnd gnd q1 p/en gnd q3 q*2 nc feedback ref_sel sync[0] vcc (an) rc1 gnd (an) sync[1] 5 6 7 8 9 10 11 25 24 23 22 21 20 19 ts88915t (top view) oe/rst vcc vcc 2x_q gnd q5 q4 freq_sel gnd gnd pll_en q0 q1 vcc 12 13 14 15 16 17 18 4 3 2 1 28 27 26 q/2 gnd q3 vcc q2 gnd lock
4 0854b?hirel?07/07 ts88915t e2v semiconductors sas 2007 3. signal description 4. scope this drawing describes the specific requirements for the clock driver ts88915t, in compliance with mil-std-883 class b or e2v standard screening. 5. applicable documents 1. mil-std-883: test methods and procedures for electronics. 2. mil-prf-38535 appendix a: general specifications for microcircuits. the microcircuits are in accordance with the applicable documents and as specified herein. 5.1 design and construction 5.1.1 terminal connections depending on the package, the terminal connections shall be as shown in figure 2-1 and figure 2-2 . 5.1.2 lead material and finish lead material and finish shall be as specified in mil-std-1835 (see section 10. on page 17 ). 5.1.3 package the macrocircuits are packaged in hermetically seal ed ceramic packages, which conform to case out- lines of mil-std-1835, but ?package mechanical data? on page 17 . the precise case outlines are described at the end of the specification (see ?package mechanical data? on page 17 8) and into mil-std-1835. table 3-1. signal index pin name num i/o signal function sync[0] 1 input reference clock input sync[1] 1 input reference clock input ref_sel 1 input chooses reference between sync[0] and sync[1] freq_sel 1 input doubles vco internal frequency feedback 1 input feedback input to phase detector rc1 1 input input for external rc network q(0-4) 5 output clock output (locked to sync) q5 1 output inverse of clock output 2x_q 1 output 2 x clock output (q) frequency (synchronous) q/2 1 output clock output (q) frequency 2 (synchronous) lock 1 output indicates phase lock has been achieved (high when locked) oe /rst 1 input output enable/asynchronous reset (active low) pll_en 1 input disables phase-lock for low frequency testing vcc, gnd 11 power power and ground pins pins 8 and 10 are ?analog? supply pins for internal pll only
5 0854b?hirel?07/07 e2v semiconductors sas 2007 ts88915t 5.2 absolute maximum ratings stresses above the absolute maximum rating ma y cause permanent damage to the device. extended operation at the maximum le vels may degrade perform ance and affect reliability. note: functional operating conditions are given in ac and dc electrical specifications. stresses beyond the absolute maximums listed may affect device reliability or cause permanent damage to the device. caution: input voltage must not be greater than the supply vo ltage by more than 2.5v at all times including during power-on reset. 5.3 mechanical and environment the microcircuits shall meet all environmental requirements of either mil-std-883 for class b devices or for e2v standard screening. 5.4 marking the document that defines the markings is identified in the related reference documents. each microcir- cuit is legible and permanently marked with the following information as minimum: e2v logo manufacturer?s part number class b identification date-code of inspection lot esd identifier if available country of manufacturing 6. electrical characteristics 6.1 general requirements all static and dynamic electrical characteristics specified for inspection purposes and the relevant mea- surement conditions are given below: table static electrical characteristics for the electrical variants table dynamic electrical characteristics for ts88915t (70 mhz and 100 mhz versions) table 5-1. absolute maximum rating for the ts88915t parameter symbol min max unit supply voltage v cc -0.5 6.0 v input voltage v in -0.5 v cc + 0.5 v storage temperature range t stg -65 +150 c power dissipation pga package ldcc package p d 500 mw thermal resistance junction-case pga29 ldcc28 jc - - 7 7 c/w
6 0854b?hirel?07/07 ts88915t e2v semiconductors sas 2007 6.2 static characteristics notes: 1. i ol and i oh are 12 ma and -12 ma respectively for the lock output. 2. the pll_en input pin is not guar anteed to meet this specification. 3. maximum test duration is 2.0 ms, one output loaded at a time. 4. specification value for static tests at 25 c and at minimum rated operating temperature. 5. specification value for static tests at maximum rated operating temperature. 6. specifications values which can be used for compability with the power pc. note: 1. pd 1 and pd 2 mw/output are for a ?q? output. 6.3 dynamic characteristics (tc = -55 c to +125 c, vcc = 5.0v 5%) note: 1. maximum operating frequency is guaranteed with the pa rt in a phase-locked condition, and all outputs loaded with 50 ? ter- minated to v cc /2. table 6-1. dc electrical characteristics (v oltages referenced to gnd) t c = -55 c to +125 c for 70 mhz and 100 mhz version; vcc = 5.0v 5% symbol parameter test conditions limits unit v ih minimum high-level input voltage v out = 0.1v or v cc - 0.1v 2.0 v v il maximum low-level input voltage v out = 0.1v or v cc - 0.1v 0.8 v v oh minimum high-level output voltage v in = v ih or v il , i oh = -36 ma (1) v ccmin v ccmax 4.01 4.51 v v ol maximum low-level output voltage v in = v ih or v il , i ol = 36 ma (1) v in = v ih or v il , i ol = 15 ma (6) 0.44 (4) 0.50 (5) 0.20 v i in maximum input leakage current v i = v cc or gnd, v ccmax 1.0 a i cct maximum i cc /input v i = v cc - 2.1v, v ccmax 2.0 (2) ma i cc maximum quiescent supply current (per package) v i = v cc or gnd, v ccmax 1.0 ma i oz maximum tri -state leakage current v i = v ih or v il ,v o = v cc or gnd, v ccmax $ 50 a table 6-2. capacitance and power specifications symbol parameter typical values unit conditions c in input capacitance 10 pf v cc = 5.0v c pd power dissipation capacitance 40 pf v cc = 5.0v pd 1 power dissipation at 50 mhz with 50 ? thevenin termination 23 mw/output 184 mw/device mw v cc = 5.0v t = 25 c pd 2 power dissipation at 50 mhz with 50 ? parallel termination to gnd 57 mw/output 456 mw/device mw v cc = 5.0v t = 25 c 6.3.1 frequency specifications symbol parameter guaranteed minimum unit 88915t-70 88915t-100 f max (1) maximum operating frequency (2x_q output) 70 100 mhz maximum operating frequency (q0-q4, q5 outputs) 35 50 mhz
7 0854b?hirel?07/07 e2v semiconductors sas 2007 ts88915t notes: 1. these t cycle minimum values are valid when ?q? output is feed back and connected to the feedback pin. 2. information in table 3-1 and in note 3 of the ac specification notes de scribe this specification and its limits depending on what output is feed back, and if freq_sel is high or low. table 6-3. sync input timing requirements symbol parameter minimum maximum unit 88915t-70 88915t-100 t rise/fall , sync inputs rise/fall time, sync inputs from 0.8 to 2.0v ? ? 3.0 ns t cycle , sync inputs input clock period, sync inputs 28.5 (1) 20.0 (1) 200 (2) ns duty cycle sync inputs input duty cycle, sync inputs 50% 25% table 6-4. ac characteristics (t c = -55 c to +125 c, v cc = 5.0v 5%, load = 50 ? terminated to v cc /2) symbol parameter min max unit conditions t rise/fall outputs rise/fall time, all outputs (between 0.2 v cc and 0.8 v cc ) 1.0 2.5 ns into a 50 ? load terminated to v cc /2 t rise/fall (1) 2x_q output rise/fall time into a 20 pf load, with termination (2) 0.5 1.6 ns t rise : 0.8v - 2.0v t fall : 2.0v - 0.8v t pulse width (1) (q0-q4, q5 , q/2) output pulse width: q0, q1, q2, q3, q4, q5, q/2 at v cc /2 0.5t cycle - 0.5 (2) 0.5t cycle + 0.5 (2) ns into a 50 ? load terminated to v cc /2 t pulse width (1) (2x_q output) output pulse width: 2x_q at 1.5v 40 mhz 50 mhz 66 mhz 100 mhz 0.5t cycle - 1.5 (2) 0.5t cycle - 1.0 0.5t cycle - 0.5 0.5t cycle - 0.5 0.5t cycle + 1.5 (2) 0.5t cycle + 1.0 0.5t cycle + 0.5 0.5t cycle + 0.5 ns must use termination (2) t pulse width (1) (2x_q output) output pulse width: 2x_q at v cc /2 40-49 mhz 50-65 mhz 66-100 mhz 0.5t cycle - 1.5 (2) 0.5t cycle - 1.0 0.5t cycle - 0.5 0.5t cycle + 1.5 (2) 0.5t cycle + 1.0 0.5t cycle + 0.5 ns into a 50 ? load terminated to v cc /2 t pd (1)(3) sync feedback sync input to feedback delay (measured at sync0 or 1 and feedback input pins) 70 mhz 100 mhz (with 1 m ? from rc1 to an v cc ) ns see note 4 and figure 7-2 for detailed explanation -1.05 -0.40 -1.05 -0.30 (with 1 m ? from rc1 to an gnd) +1.25 +3.25 t skewr (1)(4) (rising) (5) output-to-output sk ew between outputs q0-q4, q/2 (rising edges only) ?500ps all outputs into a matched 50 ? load terminated to v cc /2 t skewf (1)(4) (falling) output-to-output sk ew between outputs q0-q4 (falling edges only) ?750ps all outputs into a matched 50 ? load terminated to v cc /2 t skewall (1)(4) (falling) output-to-output sk ew 2x_q, q/2, q0- q4 rising, q5 falling ?750ps all outputs into a matched 50 ? load terminated to v cc /2
8 0854b?hirel?07/07 ts88915t e2v semiconductors sas 2007 notes: 1. these specifications are not tested, they are guaranteed by statistical characterization. see general ac specification note 1. 2. t cycle in this specification is 1/frequency at which the particular output is running. 3. the t pd specification?s min/max values may shift closer to zero of a larger pull up resistor is used. 4. under equally loaded conditions and at a fixed temperature and voltage. 5. with v cc fully powered-on, and an output properl y connected to the feedback pin. t lock maximum is with c1 = 0.1 f, t lock minimum is with c1 = 0.01 f. figure 6-1. output/input switching waveforms and timing diagrams (these waveforms represent the hook-up configuration of figure 7-4 ) t lock (5) time required to acquire phase-lock from time sync inputs signal is received 1.0 10 ms also time to lock indicator high t pzl output enable time oe /rst to 2x_q, q0-q4, q5 and q/2 3.0 14 ns measured with the pll_en pin low t phz , t plz output disable time oe /rst to 2x_q, q0-q4, q5 and q/2 3.0 14 ns measured with the pll_en pin low table 6-4. ac characteristics (t c = -55 c to +125 c, v cc = 5.0v 5%, load = 50 ? terminated to v cc /2) (continued) symbol parameter min max unit conditions t skewall t skewr t skewf t skewr sync input (sync[1] or sync[0]) feedback input q/2 output q0-q4 outputs q5 output 2x_q output t cycle sync input t pd t cycle "q" outputs
9 0854b?hirel?07/07 e2v semiconductors sas 2007 ts88915t 7. application information 7.1 general ac sp ecification notes 1. several specifications can only be measured when the ts88915t is in phase-locked operation. ts88915t units are fabricated with key transistor properties intentionally varied to create a 14 cell designed experimental matrix. 2. these two specs (t rise/fall and t pulse width 2x_q output) guarantee that the ts88915t meets the 33 mhz ts68040 p-clock input specification (at 66 mhz). for these two specs to be guar- anteed by e2v, the termination scheme shown below in figure 7-1 must be used. figure 7-1. ts68040 p-clock input termination scheme 3. to meet the 25 mhz ts68040 p-clock input specification (2 x q tpulse width at 50 mhz) freq- sel must be low. this configuration improve the accuracy of the 88915t duty cycle. 4. the wiring diagrams and explanations in figure 7-4 , figure 7-5 and figure 7-6 demonstrate the input and output frequency relationships for three possible feedback configurations. the allow- able sync input range for each case is also indicated. there are two allowable sync frequency ranges, depending whether freq_sel is high or low. although not shown, it is pos- sible to feed back the q5 output, thus creating a 180 phase shift between the sync input and the ?q? outputs. table 7-1 below summarizes the allowable sync frequency range for each possible configuration. ts88915 2x_q output ts68040 p_clock input rs z0 (clock trace) rp rp = 1.5z0 rs = z0-7 ? table 7-1. allowable sync input frequency range for different feedback configurations freq_sel level feedback output allowable sync input frequency range (mhz) corresponding vco frequency range phase relationships of the ?q? outputs to rising sync edge high high high high q/2 any ?q? (q0-q4) q5 2x_q 5 to (2x_q fmax spec)/4 10 to (2x_q fmax spec)/2 10 to (2x_q fmax spec)/2 20 to (2x_q fmax spec) 20 to (2x_q fmax spec) 20 to (2x_q fmax spec) 20 to (2x_q fmax spec) 20 to (2x_q fmax spec) 0 0 180 0 low low low low q/2 any ?q? (q0-q4) q5 2x_q 2.5 to (2x_q fmax spec)/8 5 to (2x_q fmax spec)/4 5 to (2x_q fmax spec)/4 10 to (2x_q fmax spec)/2 20 to (2x_q fmax spec) 20 to (2x_q fmax spec) 20 to (2x_q fmax spec) 20 to (2x_q fmax spec) 0 0 180 0
10 0854b?hirel?07/07 ts88915t e2v semiconductors sas 2007 5. a 1 m ? resistor tied to either analog v cc or analog gnd as shown in figure 7-1 is required to ensure no jitter is present on the ts88915t ou tputs. this technique causes a phase offset between the sync input and the output connected to the feedback input, measured at the input pins. the t pd spec describes how this offset varies with process, temperature and volt- age. the specs are arrived at by measuring the phase relationship for the 14 lots described in note 1 while the part was in phase-locked operation. the actual measurements are made with 10 mhz sync input (1.0 ns edge rate from 0.8v - 2.0v) with the q/2 output feed back. the phase measurements are made at 1.5v. the q/2 output is terminated at the feedback input with 100 ? to v cc and 100 ? to gnd. figure 7-2. depiction of the fixed sync to feedback offset (t pd ) which is present when a 1 m ? resistor is tied to v cc or gnd 6. the t skewr specification guarantees that the rising edges of outputs q/2, q0, q1, q2, q3 and q4 will always fall within a 500 ps window within one part. however, if the relative position of each output within this window is not specif ied, the 500 ps window must be added to each side of the t pd specification limits to calcul ate the total part-to-part skew. for this reason the absolute distribution of these outputs is provided in table 7-2 . when taking the skew data, q0 was used as a reference, so all measurements are relative to this output. the information in table 7-2 is derived from measurements taken from the 14 process lots described in note 1, over the tem- perature and voltage range. external loop filter rc1 r2 330 ? c1 0.1 f analog gnd 1 m ? reference resistor 1 m ? reference resistor rc1 330 ? 0.1 f c1 sync input feedback output 3.0v 5.0v 2.25 ns offset sync input feedback output -0.775 ns offset 3.0v 5.0v with the 1 m ? resistor tied in this fashion, the t pd specification measured at the input pins is: t pd = 2.25 ns 1.0 ns with the 1 m ? resistor tied in this fashion, the t pd specification measured at the input pins is: t pd = -0.775 ns 0.275 ns r2
11 0854b?hirel?07/07 e2v semiconductors sas 2007 ts88915t 7. calculation of total output-to-output skew between multiple parts (part-to-part skew) by combining the t pd specification and the information in note 5, the worst case output-to-out- put skew between multiple ts88915?s connected in parallel can be calculated. this calculation assumes that all parts have a common sync input clock with equal delay that input signal to each part. this skew value is valid at the ts88915 output pins only (equally loaded), it does not include pcb trace delays due to varying loads.with a 1 m ? resistor tied to analog vcc as shown in note 4, the t pd spec. limits between sync and the q/2 output (connected to the feedback pin) are -1.05 ns and -0.5 ns. to calculate the skew of any given output between two or more parts, the absolute value of the distribution of that output given in table 7-2 must be subtracted and added to the lower and upper t pd spec limits respectively. for output q2, [276-(-44)] = 320 ps is the absolute value of the distribution. therefore [-1.05 - 0.32] = -1.37 ns is the lower t pd limit, and [-0.5 + 0.32] = -0.18 ns is the upper limit. therefore the worst case skew of output q2 between any number of part is [(-1.37)-(-0.18)] = 1.19 ns. q2 has the worst case skew distribution of any output, so 1.2 ns is the absolute worst case output-to-output skew between multiple parts. 8. note 4 explains that the t pd specification was measured and is guaranteed for the configuration of the q/2 output connected to the feedback pin and the sync input running at 10 mhz. the fixed offset (t pd ) as described above has some dependence on the input frequency and what frequency the vco is running. the graphs of figure 7-2 demonstrate this dependence. the data presented in figure 7-2 is from devices representing process extremes, and the measure- ments were also taken at the voltage extremes (v cc = 5.25v and 4.75v). therefore the data in figure 7-2 is a realistic representation of the variation of t pd . table 7-2. relative position of outputs q/2, q0-q4, 2x_q,within the 500 ps t skewr spec window output - (ps) + (ps) q0 q1 q2 q3 q4 q/2 2x_q 0 -72 -44 -40 -274 -16 -633 0 40 275 255 -34 250 -35
12 0854b?hirel?07/07 ts88915t e2v semiconductors sas 2007 figure 7-3. 9. the lock indicator pin (lock) will reliably indi cate a phase-locked cond ition at sync input fre- quencies down to 10 mhz. at frequencies below 10 mhz, the frequency of correction pulses going into the phase detector from the sync and feedback pins may not be sufficient to allow the lock indicator circuitry to accurate ly predict a phase-locked condition. the ts88915t is guaranteed to provide stable phase-locked operation down to the appropriate minimum input frequency given in table 7-1 , even though the lock pin may be low at frequencies below 10 mhz. 7.2 timing notes 1. the ts88915t aligns rising edges of the feedback input and the sync input, therefore the sync input does not require a 50% duty cycle. 2. all skew specs are measured between v cc /2 crossing point of the appropriate output edges. all skews are specified as ?windows?, not as a ?deviation around a center point?. 3. if a ?q? output is connected to the feedback input (this situation is not shown), the ?q? output frequency would match the sync input frequency, the 2x_q output would run twice the sync frequency, and the q/2 output would run at half the sync frequency. see figure 7-3 , figure 7- 4 and figure 7-5 below. tpd versus frequency for q/2 output feed back, including process and voltage variation at 25?c (with 1 m ? resistor tied to analog vcc) tpd versus frequency for q4 output feed back, including process and voltage variation at 25?c (with 1 m ? resistor tied to analog vcc) tpd versus frequency for q/2 output feed back, including process and voltage variation at 25?c (with 1 m ? resistor tied to analog gnd) tpd versus frequency for q4 output feed back, including process and voltage variation at 25?c (with 1 m ? resistor tied to analog gnd) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 2.5 5.0 7.5 10.0 12.5 15.0 17.5 2.5 5.0 7.5 10.0 12.5 15.0 17.5 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 5 10 15 20 25 tpd sync to feedback (ns) tpd sync to feedback (ns) tpd sync to feedback (ns) tpd sync to feedback (ns) -0.50 -0.75 -1.00 -1.25 -1.50 -0.50 -1.00 -1.50 -2.00 2.5 5.0 7.5 10 12.5 15 17.5 20 22.5 25 27.5 sync input frequency (mhz) sync input frequency (mhz) sync input frequency (mhz) sync input frequency (mhz)
13 0854b?hirel?07/07 e2v semiconductors sas 2007 ts88915t figure 7-4. wiring diagram and frequency relationship with q/2 output feed back figure 7-5. wiring diagram and frequency relationship with q4 output feed back figure 7-6. wiring diagram and frequency relationship with 2x_q output feed back 25 mhz feedback signal 100 mhz signal crystal osc. external loop filter 25 mhz input low 50 mhz "q" clock outputs high high high feedback ref_sel sync[0] analog vcc rc1 analog gnd fq_sel q0 q1 pll_en q/2 q3 q2 rst q5 q4 2x_q 50 mhz feedback signal 100 mhz signal crystal osc. external loop filter 50 mhz input low 50 mhz "q" clock outputs high high high feedback ref_sel sync[0] analog vcc rc1 analog gnd fq_sel q0 q1 pll_en q/2 q3 q2 rst q5 q4 2x_q 25 mhz signal 100 mhz feedback signal crystal osc. external loop filter 100 mhz input low 50 mhz "q" clock outputs high high high feedback ref_sel sync[0] analog vcc rc1 analog gnd fq_sel q0 q1 pll_en q/2 q3 q2 rst q5 q4 2x_q 25 mhz signal
14 0854b?hirel?07/07 ts88915t e2v semiconductors sas 2007 7.3 notes concerning loop filter and b oard layout issues 1. figure 7-6 shows a loop filter and analog isolation scheme which will be effective in most appli- cations. the following guidelines should be followed to ensure stable and jitter-free operation: 2. all loop filter and analog isolation components should be tied as close to the package as possi- ble. stray current passing through the parasitics of long traces can cause undesirable voltage transients at the rc1 pin. 3. the 47 ? resistors, the 10 f low frequency bypass capacitor, and the 0.1 f high frequency bypass capacitor form a wide bandwidth filter th at will minimize the 88915t? s sensitivity to volt- age transients from the system digital v cc supply and ground planes. this filter will typically ensure that a 100 mv step deviation on the digital v cc supply will cause no more than 100 ps phase deviation on the 88915t outputs. a 250 mv step deviation on v cc using the recom- mended filter values should cause no more than a 250 ps phase deviation; if a 25 f bypass capacitor is used (instead of 1 f) a 250 mv v cc step should cause no more than a 100 ps phase deviation. if good bypass techniques are used on a board design near components which may cause digital v cc and ground noise, the above described v cc step deviations should not occur at the 88915t?s digital v cc supply. the purpose of the bypass filtering scheme shown in figure 7-6 is to give the 88915t additional protection from the power supply and ground plane transients that can occur in a high frequency, high speed digital system. 4. there are no special requirements set forth for the loop filter resistors (1 m ? and 330 ? ). the loop filter capacitor (0.1 f) can be a ceramic chip capacitor, the same as a standard bypass capacitor. 5. the 1 m ? reference resistor injects current into the internal charge pump of the pll, causing a fixed offset between the outputs and the sync input. this also prevents excessive jitter caused by inherent pll dead-band. if the vco (2x_q output) is running above 40 mhz, the 1 m ? resistor provides the correct amount of current injection into the charge pump (2-3 a). for the 70 and 100 mhz versions, if the vco is running below 40 mhz, a 1.5 m ? resistor should be used (instead of 1 m ? ). 6. in addition to the bypass capacitors used in the analog filter of figure 7-6 , there should be a 0.1 f bypass capacitor between each of the other (digital) four v cc pins and the board ground plane. this will reduce output switching noise ca used by the 88915t ou tputs, in addition to reducing potential for noise in the ?analog? section of the chip. these bypass capacitors should also be tied as close to the package as possible. figure 7-7. recommended loop filter and analog isolation scheme for the ts88915t note: a separate analog power supply is not necessary and should not be used. following these prescribed guidelines is all that is necessary to use the ts88915t in a normal digital environment. board v cc 1 m ? 47 ? 47 ? analog loop filter/fco section of the ts88915t (not drawn to scale) analog v cc analog gnd rc1 330 ? 10 f low freq bypass 0.1 f high freq bypass
15 0854b?hirel?07/07 e2v semiconductors sas 2007 ts88915t figure 7-8. representation of a potential multi-processing application utilizing the ts88915t for fre- quency multiplication and low board-to-board skew 7.4 ts88915t system level testing functionality tri-state functionality has been added to the ts88915t to ease system board testing. bringing the oe /rst pin low will put all outputs (except for lock) in to a high impedance st ate. as long as the pll_en pin is low, the q0-q4, q5 and q/2 outputs will remain in the low state after the oe /rst until a falling sync edge is seen. the 2x_q output will be the inverse of the sync signal in this mode. if the tri-state functionality will be used, a pull-up or a pull-down resistor must be tied to the feedback input pin to prevent it from floating when the feedback output goes into high impedance. with the pll_en pin low the selected sync signal is gated directly into the signal clock distribution net- work, bypassing and disabling the vc o. in this mode the outputs are directly driven by the sync input (per the block diagram). this mode can also be used for low frequency board testing. note: if the outputs are put into 3-state during normal pll operation, the loop will be broken and phase-lock will be lost. it will take a maximum of 10 ms (t lock spec) to regain phase-lock after the oe /rst pin goes back high. cmmu cmmu cpu cmmu cmmu cmmu clock at f pll 2f ts88915t cmmu cmmu cpu cmmu cmmu cmmu pll 2f ts88915t cpu card system clock source distribute clock at f clock at 2f at point of use cpu card pll 2f ts88915t memory control clock at 2f at point of use memory cards
16 0854b?hirel?07/07 ts88915t e2v semiconductors sas 2007 8. preparation for delivery 8.1 packaging microcircuits are prepared for delivery in accordance with mil-prf-38535. 8.2 certificate of compliance e2v offers a certificate of compliances with each shipment of parts, affirming the products are in compli- ance either with mil-std-883 and guarantying the parameters not tested at temperature extremes for the entire temperature range. 9. handling mos devices must be handled with certain precautions to avoid damage due to accumulation of static charge. input protection devices have been designed in the chip to minimize the effect of this static buildup. however, the following handling practices are recommended: devices should be handled on benches with conductive and grounded surfaces ground test equipment, tools and operator do not handle devices by the leads. store devices in conductive foam or carriers. avoid use of plastic, rubber, or silk in mos areas. maintain relative humidity above 50 percent if practical.
17 0854b?hirel?07/07 e2v semiconductors sas 2007 ts88915t 10. package mechanical data 10.1 29-pin pga dim inches millimeters min max min max a 0.594 0.606 15.087 15.392 c - 0.107 - 2.72 d 0.17 0.19 4.32 4.83 e 0.045 0.055 1.143 1.397 f 0.045 0.055 1.143 1.397 g 0.100 bsc 2.54 bsc h 0.017 0.019 0.43 0.48
18 0854b?hirel?07/07 ts88915t e2v semiconductors sas 2007 10.2 28-pin ldcc note: this package is pin compatible with plcc 11. ordering information notes: 1. for availability of the different versions, contact your local e2v sales office. 2. the letter x in the part number designat es a "prototype" product that has not been qualified by e2v. reliability of a tsx par t- number is not guaranteed and such part-number shall not be us ed in flight hardware. product changes may still occur while shipping prototypes. 12. document revision history table 12-1 provides a revision history for this hardware specification. m: -55/+125?c v: -40/+85?c r: pga w: ldcc ts xx 88915t part identifier product code (1) ts(x) (2) 88915 temperature range (1) screening level maximum output frequency x x nnn (1) package 70: 70 mhz 100: 100 mhz blank: standard b/t: according to mil-std-883 d/t: burn-in table 12-1. document revision history revision number date su bstantive change(s) b 06/2007 name change from atmel to e2v ordering information update a 06/2002 initial revision
whilst e2v has taken care to ensure the accuracy of the info rmation contained herein it accept s no responsibility for the conse quences of any use thereof and also reserves the right to change the specific ation of goods without notice. e2v accepts no liability beyond th at set out in its stan- dard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in acc ordance with informa- tion contained herein. how to reach us home page: www.e2v.com sales office: northern europe e2v ltd 106 waterhouse lane chelmsford essex cm1 2qu england tel: +44 (0)1245 493493 fax: +44 (0)1245 492492 e-mail: enquiries@e2v.com southern europe e2v sas 16 burospace f-91572 bivres cedex france tel: +33 (0) 16019 5500 fax: +33 (0) 16019 5529 e-mail: enquiries-fr@e2v.com germany and austria e2v gmbh industriestra?e 29 82194 gr?benzell germany tel: +49 (0) 8142 41057-0 fax: +49 (0) 8142 284547 e-mail: enquiries-de@e2v.com americas e2v inc. 4 westchester plaza elmsford ny 10523-1482 usa tel: +1 (914) 592 6050 or 1-800-342-5338, fax: +1 (914) 592-5148 e-mail: enquiries-na@e2v.com asia pacific e2v bank of china tower 30th floor office 7 1 garden rd central hong kong tel: +852 2251 8227/8/9 fax: +852 2251 8238 e-mail: enquiries-hk@e2v.com product contact: e2v avenue de rochepleine bp 123 - 38521 saint-egrve cedex france tel: +33 (0)4 76 58 30 00 hotline : std-hotline@e2v.com 0854b?hirel?07/07 e2v semiconductors sas 2007

▲Up To Search▲

Price & Availability of TS88915TMWDT70

	To Download TS88915TMWDT70 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .